The present invention relates to a digital VLSI circuit with low power consumption, especially digital VLSI circuit with contemplated power saving by controlling clock signal supply and power supply by a plurality of inner arithmetic operation units executing pipeline arithmetic processing and relates to digital VLSI circuit with contemplated power saving by feedback control or feedforward control of operating power voltage, board bias voltage and operating frequency.
Moreover the invention relates to image processing system and mobile terminal into which the digital VLSI circuit with low power consumption is incorporated.